Sciweavers

689 search results - page 12 / 138
» Proposal of High Level Architecture Extension
Sort
View
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
15 years 3 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
ISCAPDCS
2007
14 years 11 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
IPPS
2006
IEEE
15 years 3 months ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
TVLSI
2010
14 years 4 months ago
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
Hamed F. Dadgour, Kaustav Banerjee
TVLSI
2008
144views more  TVLSI 2008»
14 years 9 months ago
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective
Abstract--Embedded systems present significant security challenges due to their limited resources and power constraints. This paper focuses on the issues of building secure embedde...
Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-...