Sciweavers

689 search results - page 17 / 138
» Proposal of High Level Architecture Extension
Sort
View
87
Voted
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
15 years 4 months ago
System Level Design Space Exploration for Multiprocessor System on Chip
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha...
INFORMATICALT
2007
136views more  INFORMATICALT 2007»
14 years 9 months ago
Generic Multimedia Database Architecture Based upon Semantic Libraries
Semantic-based storage and retrieval of multimedia data requires accurate annotation of the data. Annotation can be done either manually or automatically. The retrieval performance...
Omara Abdul Hamid, Muhammad Abdul Qadir, Nadeem If...
SIGOPS
2011
255views Hardware» more  SIGOPS 2011»
14 years 4 months ago
Bridging functional heterogeneity in multicore architectures
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
Dheeraj Reddy, David A. Koufaty, Paul Brett, Scott...
AFRICACRYPT
2010
Springer
15 years 4 months ago
Avoiding Full Extension Field Arithmetic in Pairing Computations
Abstract. The most costly operations encountered in pairing computations are those that take place in the full extension field Fpk . At high levels of security, the complexity of ...
Craig Costello, Colin Boyd, Juan Manuel Gonz&aacut...
ICPP
2008
IEEE
15 years 4 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...