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» Proposal of High Level Architecture Extension
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EUROPAR
2010
Springer
14 years 10 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
ICRA
1998
IEEE
163views Robotics» more  ICRA 1998»
15 years 1 months ago
A Multi-Loop Robust Navigation Architecture for Mobile Robots
This paper describes a multi-loop, modular navigation architecture for mobile robots whose structure allows the execution of most types of navigation tasks in a highly robust mann...
José Castro, Vítor Santos, M. Isabel...
ICDE
2010
IEEE
224views Database» more  ICDE 2010»
14 years 10 months ago
Partitioning real-time ETL workflows
—Many organizations are aiming to move away from traditional batch processing ETL to real-time ETL (RT-ETL). This move is motivated by a need to analyze and take decisions on as ...
Alkis Simitsis, Chetan Gupta, Song Wang, Umeshwar ...
ICCCN
2007
IEEE
15 years 1 months ago
A Unified Software Architecture to Enable Cross-Layer Design in the Future Internet
While research on cross-layer network optimization has been progressing, useful implementations have been lagging because the current Internet architecture does not accommodate cro...
Ilia Baldine, Manoj Vellala, Anjing Wang, George N...
INFOCOM
1996
IEEE
15 years 1 months ago
Maintaining High Throughput during Overload in ATM Switches
This report analyzes two popular heuristics for ensuring packet integrity in ATM switching systems. In particular, we analyze the behavior of packet tail discarding, in order to u...
Jonathan S. Turner