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» Proposal of High Level Architecture Extension
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MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
15 years 4 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
15 years 4 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ICSE
2010
IEEE-ACM
15 years 2 months ago
Providing support for creating next generation software architecture languages
Many languages for software architectures have been proposed, each dealing with different stakeholder concerns, operating at different levels of abstraction and with different deg...
Ivano Malavolta
ANCS
2006
ACM
15 years 3 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...
PRDC
2006
IEEE
15 years 3 months ago
SEVA: A Soft-Error- and Variation-Aware Cache Architecture
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai