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» Proposal of High Level Architecture Extension
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DAC
2007
ACM
15 years 10 months ago
Automatic Verification of External Interrupt Behaviors for Microprocessor Design
Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This pap...
Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 2 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ASAP
2004
IEEE
123views Hardware» more  ASAP 2004»
15 years 1 months ago
A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these al...
Fabien Castanier, Alberto Ferrante, Vincenzo Piuri
ICRA
2009
IEEE
147views Robotics» more  ICRA 2009»
15 years 4 months ago
Equipping robot control programs with first-order probabilistic reasoning capabilities
— An autonomous robot system that is to act in a real-world environment is faced with the problem of having to deal with a high degree of both complexity as well as uncertainty. ...
Dominik Jain, Lorenz Mösenlechner, Michael Be...
CNSR
2008
IEEE
140views Communications» more  CNSR 2008»
15 years 4 months ago
An Approach for Optimal Bandwidth Allocation in Packet Processing Systems
The increasing demand for more bandwidth and the increased application variety fuel the need for high performance network processors. A simple but highly repetitive task performed...
Mahmood Ahmadi, Stephan Wong