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» Proposal of High Level Architecture Extension
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ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
14 years 7 months ago
Mitigation of intra-array SRAM variability using adaptive voltage architecture
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
Ashish Kumar Singh, Ku He, Constantine Caramanis, ...
MICRO
2007
IEEE
135views Hardware» more  MICRO 2007»
15 years 4 months ago
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a sing...
Christophe Dubach, Timothy M. Jones, Michael F. P....
CISIS
2010
IEEE
15 years 3 months ago
Resilient Critical Infrastructure Management Using Service Oriented Architecture
—The SERSCIS project aims to support the use of interconnected systems of services in Critical Infrastructure (CI) applications. The problem of system interconnectedness is aptly...
Martin Hall-May, Mike Surridge
ICASSP
2008
IEEE
15 years 4 months ago
Analyzing the scalability of SIMD for the next generation software defined radio
Previous studies have shown that wireless DSP algorithms exhibit high levels of data level parallelism (DLP). Commercial and research work in the field of software defined radio...
Mark Woh, Yuan Lin, Sangwon Seo, Trevor N. Mudge, ...
APCCAS
2006
IEEE
304views Hardware» more  APCCAS 2006»
15 years 3 months ago
Low-Power Bus Transform Coding for Multilevel Signals
Abstract— In this paper, we propose a novel extension of BusInvert coding to handle 4-level pulse amplitude modulated (PAM-4) signals. A generalized mathematical model for energy...
Fakhrul Zaman Rokhani, Gerald E. Sobelman