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» Protocol Implementation Using Integrated Layer Processing
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CCGRID
2001
IEEE
15 years 5 months ago
Parallel I/O Support for HPF on Clusters
Clusters of workstations are a popular alternative to integrated parallel systems designed and built by a vendor. Besides their huge cumulative processing power, they also provide...
Peter Brezany, Viera Sipková
DATE
2007
IEEE
125views Hardware» more  DATE 2007»
15 years 7 months ago
Simulation platform for UHF RFID
1 Developing modern integrated and embedded systems require well-designed processes to ensure flexibility and independency. These features are related to exchangeability of hardw...
Vojtech Derbek, Christian Steger, Reinhold Weiss, ...
HICSS
2003
IEEE
136views Biometrics» more  HICSS 2003»
15 years 6 months ago
Increasing Understanding of the Modern Testing Perspective in Software Product Development Projects
Testing can be difficult to integrate into software development. Approaches to software testing in relation to implementing software are based on the V-model of testing. The softw...
Maaret Pyhäjärvi, Kristian Rautiainen, J...
ICSEA
2008
IEEE
15 years 8 months ago
Reuse through Requirements Traceability
The Reuse of code artefacts can make development quicker, cheaper and more robust, but the process is complex and has many pitfalls: Code artefacts must exist, be available, be fo...
Rob Pooley, Craig Warren
GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
15 years 6 months ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...