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GLOBECOM
2006
IEEE
15 years 3 months ago
Implementation of a Coded Modulation for Deep Space Optical Communications
— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed thi...
Michael K. Cheng, Bruce E. Moision, Jon Hamkins, M...
IJCAI
2003
14 years 11 months ago
Aggregate Functions in Disjunctive Logic Programming: Semantics, Complexity, and Implementation in DLV
Disjunctive Logic Programming (DLP) is a very expressive formalism: it allows to express every property of finite structures that is decidable in the complexity class ¡£¢¤ (...
Tina Dell'Armi, Wolfgang Faber, Giuseppe Ielpa, Ni...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 3 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
JPDC
2006
112views more  JPDC 2006»
14 years 9 months ago
CEFT: A cost-effective, fault-tolerant parallel virtual file system
The vulnerability of computer nodes due to component failures is a critical issue for cluster-based file systems. This paper studies the development and deployment of mirroring in...
Yifeng Zhu, Hong Jiang
71
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
High performance support of parallel virtual file system (PVFS2) over Quadrics
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...
Weikuan Yu, Shuang Liang, Dhabaleswar K. Panda