533 search results - page 10 / 107 » Protocol synthesis from timed and structured specifications |
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
ISSS
1999
IEEE
15 years 1 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
105
Voted
INTEGRATION
2008
14 years 9 months ago
2008
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
VLSID
1994
IEEE
15 years 1 months ago
1994
IEEE
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...