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» Protocol verification using flows: An industrial experience
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WSC
1996
14 years 11 months ago
Supporting Manufacturing with Simulation: Model Design, Development, and Deployment
In this paper, we identify and discuss the features we believe are key to the successful use of simulation as a manufacturing support tool. The discussion begins with three sample...
Frank Chance, Jennifer Robinson, John W. Fowler
FORMATS
2004
Springer
15 years 3 months ago
Bounded Model Checking for Region Automata
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this reg...
Fang Yu, Bow-Yaw Wang, Yao-Wen Huang
ASE
2004
167views more  ASE 2004»
14 years 9 months ago
Cluster-Based Partial-Order Reduction
The verification of concurrent systems through an exhaustive traversal of the state space suffers from the infamous state-space-explosion problem, caused by the many interleavings ...
Twan Basten, Dragan Bosnacki, Marc Geilen
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
15 years 10 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
Roopak Sinha, Partha S. Roop, Samik Basu
EMSOFT
2008
Springer
14 years 11 months ago
Randomized directed testing (REDIRECT) for Simulink/Stateflow models
The Simulink/Stateflow (SL/SF) environment from Mathworks is becoming the de facto standard in industry for model based development of embedded control systems. Many commercial to...
Manoranjan Satpathy, Anand Yeolekar, S. Ramesh