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ETS
2006
IEEE
108views Hardware» more  ETS 2006»
15 years 9 months ago
A DFT Architecture for Asynchronous Networks-on-Chip
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
Xuan-Tu Tran, Jean Durupt, François Bertran...
FPL
2009
Springer
156views Hardware» more  FPL 2009»
15 years 7 months ago
A highly scalable Restricted Boltzmann Machine FPGA implementation
Restricted Boltzmann Machines (RBMs) — the building block for newly popular Deep Belief Networks (DBNs) — are a promising new tool for machine learning practitioners. However,...
Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMaho...
CEC
2009
IEEE
15 years 7 months ago
A model for intrinsic artificial development featuring structural feedback and emergent growth
Abstract--A model for intrinsic artificial development is introduced in this paper. The proposed model features a novel mechanism where growth emerges, rather than being triggered ...
Martin Trefzer, Tüze Kuyucu, Julian Francis M...
CSFW
2010
IEEE
15 years 7 months ago
Towards a Formal Foundation of Web Security
—We propose a formal model of web security based straction of the web platform and use this model to analyze the security of several sample web mechanisms and applications. We id...
Devdatta Akhawe, Adam Barth, Peifung E. Lam, John ...
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
15 years 7 months ago
Power-aware mapping for reconfigurable NoC architectures
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
Mehdi Modarressi, Hamid Sarbazi-Azad