20 search results - page 3 / 4 » Pseudo-Random Pattern Testing of Bridging Faults |
DDECS
2007
IEEE
14 years 18 days ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
VTS
1996
IEEE
13 years 10 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
DATE
2006
IEEE
14 years 10 days ago
2006
IEEE
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
VTS
2005
IEEE
13 years 12 months ago
2005
IEEE
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
DATE
2006
IEEE
14 years 10 days ago
2006
IEEE
In this paper, we propose a new circuit transformation technique in conjunction with the use of a special diagnostic test pattern, named SO-SLAT pattern, to achieve higher multipl...