1630 search results - page 109 / 326 » Publish-Subscribe for High-Performance Computing |
142
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DAC
2001
ACM
16 years 5 months ago
2001
ACM
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
182
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VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
130
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ICCD
2004
IEEE
16 years 1 months ago
2004
IEEE
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
166
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ISCA
2009
IEEE
15 years 11 months ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
147
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SBACPAD
2006
IEEE
15 years 10 months ago
2006
IEEE
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...