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85
Voted
ICS
1995
Tsinghua U.
15 years 1 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
ASAP
2006
IEEE
15 years 4 days ago
2006
IEEE
Abstract--The growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency, pipelined...
94
Voted
EUROPAR
2008
Springer
14 years 12 months ago
2008
Springer
The Cell Broadband Engine (CBE) is a new heterogeneous multi-core processor from IBM, Sony and Toshiba, and provides the potential to achieve an impressive level of performance for...
FPL
2008
Springer
14 years 11 months ago
2008
Springer
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
99
Voted
AAAI
2010
14 years 11 months ago
2010
We present novel randomized algorithms for solving global motion planning problems that exploit the computational capabilities of many-core GPUs. Our approach uses thread and data...