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HPCC
2009
Springer
15 years 2 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
ANCS
2006
ACM
15 years 1 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
CLUSTER
2004
IEEE
15 years 1 months ago
An efficient end-host architecture for cluster communication
Cluster computing environments built from commodity hardware have provided a cost-effective solution for many scientific and high-performance applications. Likewise, middleware te...
Xin Qi, Gabriel Parmer, Richard West
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DEBS
2009
ACM
15 years 1 months ago
Event-based systems: opportunities and challenges at exascale
Streaming data models have been shown to be useful in many applications requiring high-performance data exchange. Application-level overlay networks are a natural way to realize t...
Greg Eisenhauer, Matthew Wolf, Hasan Abbasi, Karst...
CORR
2010
Springer
128views Education» more  CORR 2010»
14 years 10 months ago
A Performance Study of GA and LSH in Multiprocessor Job Scheduling
Multiprocessor task scheduling is an important and computationally difficult problem. This paper proposes a comparison study of genetic algorithm and list scheduling algorithm. Bo...
S. R. Vijayalakshmi, G. Padmavathi