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VTS
2000
IEEE
95views Hardware» more  VTS 2000»
15 years 9 months ago
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
Li Chen, Sujit Dey
BPM
2008
Springer
142views Business» more  BPM 2008»
15 years 6 months ago
Crosscutting Concern Documentation by Visual Query of Business Processes
Business processes can be very large and may contain several different concerns, scattered across the process and tangled with other concerns. Crosscutting concerns are difficult t...
Chiara Di Francescomarino, Paolo Tonella
DAC
2005
ACM
15 years 6 months ago
Performance space modeling for hierarchical synthesis of analog integrated circuits
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
Georges G. E. Gielen, Trent McConaghy, Tom Eeckela...
DAC
1999
ACM
16 years 5 months ago
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling a...
Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Ken...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
16 years 4 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran