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VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
16 years 6 months ago
A Framework for Design Space Exploration of Parameterized VLSI Systems
The paper presents two new approaches to multiobjective design space exploration for parametric VLSI systems. Both considerably reduce the number of simulations needed to determin...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
160
Voted
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
16 years 18 days ago
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Ri...
150
Voted
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
16 years 14 days ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
159
Voted
DATE
2006
IEEE
102views Hardware» more  DATE 2006»
16 years 6 days ago
Faster exploration of high level design alternatives using UML for better partitions
Partitioning is a time consuming and computationally complex optimization problem in the codesign of hardware software systems. The stringent time-to-market requirements have resu...
Waseem Ahmed, Doug Myers
ICRA
2006
IEEE
131views Robotics» more  ICRA 2006»
16 years 5 days ago
Designing Open-loop Plans for Planar Micro-manipulation
— This paper describes a test-bed for planar micro manipulation tasks and a framework for planning based on quasistatic models of mechanical systems with frictional contacts. We ...
David J. Cappelleri, Jonathan Fink, Barry Munkunda...