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PATMOS
2007
Springer
15 years 11 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
ICMCS
2006
IEEE
179views Multimedia» more  ICMCS 2006»
15 years 11 months ago
Optimizing Algorithms for Region-of-Interest Video Compression, with Application to Mobile Telehealth
Wireless communication of video poses constraints on information capacity. Region-of-Interest (ROI) video coding provides higher quality in the ROI, but poorer quality in the back...
Sira Rao, Nikil Jayant
168
Voted
KBSE
2005
IEEE
15 years 10 months ago
Prufrock: a framework for constructing polytypic theorem provers
Current formal software engineering methodologies provide a vast array of languages for specifying correctness properties, as well as a wide assortment automated tools that aid in...
Justin Ward, Garrin Kimmell, Perry Alexander
141
Voted
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 10 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
GRAPHITE
2005
ACM
15 years 10 months ago
Sketching with a low-latency electronic ink drawing tablet
Drawing on paper is an experience which is still unmatched by any input device for drawing into a computer in terms of accuracy, dexterity and general pleasantness of use. This pa...
Alex Henzen, Neculai Ailenei, Fabian Di Fiore, Fra...