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2003
IEEE
140views Hardware» more  DATE 2003»
13 years 9 months ago
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard
ng precision of abstract SystemC models using the SystemC Verification Standard Franco Carbognani1 , Christopher K. Lennard2 , C. Norris Ip3 , Allan Cochrane2 , Paul Bates2 1 Caden...
Franco Carbognani, Christopher K. Lennard, C. Norr...
SIES
2010
IEEE
13 years 2 months ago
Verification of a CAN bus model in SystemC with functional coverage
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which...
Christoph Kuznik, Gilles B. Defo, Wolfgang Mü...
MEMOCODE
2010
IEEE
13 years 2 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
FDL
2005
IEEE
13 years 9 months ago
Implementation of a SystemC based Environment
Verification and validation are key issues for today's SoC design projects. This paper presents the implementation of a SystemC based environment for transaction-based verifi...
Richard Hoffer, Frank Baszynski
EMSOFT
2010
Springer
13 years 2 months ago
PinaVM: a systemC front-end based on an executable intermediate representation
SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorpo...
Kevin Marquet, Matthieu Moy