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» Quality considerations in delay fault testing
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DATE
2010
IEEE
134views Hardware» more  DATE 2010»
15 years 2 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu
IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
15 years 1 months ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
15 years 2 months ago
TranGen: a SAT-based ATPG for path-oriented transition faults
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
Kai Yang, Kwang-Ting Cheng, Li-C. Wang
HIS
2009
14 years 7 months ago
Design Methodology of a Fault Aware Controller Using an Incipient Fault Diagonizer
The problem of failure diagnosis has received a considerable attention in the domain of reliability engineering, process control and computer science. The increasing stringent req...
Joydeb Roychoudhury, Tribeni Prasad Banerjee, Anup...
ATS
2010
IEEE
229views Hardware» more  ATS 2010»
14 years 7 months ago
Variation-Aware Fault Modeling
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, I...