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VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
16 years 2 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
15 years 10 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
126
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DSN
2008
IEEE
15 years 8 months ago
Integration and evaluation of Multi-Instance-Precommit schemes within postgreSQL
Multi-Instance-Precommit (MIP) has been recently presented as an innovative transaction management scheme in support of reliability for Atomic Transactions in multitier (e.g. Web-...
Paolo Romano, Francesco Quaglia
GLVLSI
2008
IEEE
137views VLSI» more  GLVLSI 2008»
15 years 8 months ago
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
Ann Gordon-Ross, Jeremy Lau, Brad Calder
DFT
2007
IEEE
135views VLSI» more  DFT 2007»
15 years 8 months ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon