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» Quantifiers and Working Memory
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TC
2010
14 years 8 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
SIGMOD
2006
ACM
106views Database» more  SIGMOD 2006»
15 years 10 months ago
Run-time operator state spilling for memory intensive long-running queries
Main memory is a critical resource when processing longrunning queries over data streams with state intensive operators. In this work, we investigate state spill strategies that h...
Bin Liu, Yali Zhu, Elke A. Rundensteiner
IEEEPACT
2009
IEEE
15 years 4 months ago
StealthTest: Low Overhead Online Software Testing Using Transactional Memory
—Software testing is hard. The emergence of multicore architectures and the proliferation of bugprone multithreaded software makes testing even harder. To this end, researchers h...
Jayaram Bobba, Weiwei Xiong, Luke Yen, Mark D. Hil...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
15 years 4 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
NOCS
2008
IEEE
15 years 4 months ago
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
Bart Vermeulen, Kees Goossens, Siddharth Umrani