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» Quantifiers and Working Memory
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ICS
2005
Tsinghua U.
15 years 9 months ago
A heterogeneously segmented cache architecture for a packet forwarding engine
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
Kaushik Rajan, Ramaswamy Govindarajan
CASES
2004
ACM
15 years 9 months ago
A post-compiler approach to scratchpad mapping of code
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy...
Federico Angiolini, Francesco Menichelli, Alberto ...
113
Voted
VLDB
2004
ACM
122views Database» more  VLDB 2004»
15 years 9 months ago
Cache-Conscious Radix-Decluster Projections
As CPUs become more powerful with Moore’s law and memory latencies stay constant, the impact of the memory access performance bottleneck continues to grow on relational operator...
Stefan Manegold, Peter A. Boncz, Niels Nes
WEA
2010
Springer
281views Algorithms» more  WEA 2010»
15 years 9 months ago
Distributed Time-Dependent Contraction Hierarchies
Server based route planning in road networks is now powerful enough to find quickest paths in a matter of milliseconds, even if detailed information on time-dependent travel times...
Tim Kieritz, Dennis Luxen, Peter Sanders, Christia...
130
Voted
HPCA
2002
IEEE
15 years 8 months ago
User-Level Communication in Cluster-Based Servers
Clusters of commodity computers are currently being used to provide the scalability required by severalpopular Internet services. In this paper we evaluate an efficient cluster-b...
Enrique V. Carrera, Srinath Rao, Liviu Iftode, Ric...