2555 search results - page 409 / 511 » Quantifiers and Working Memory |
126
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HPCA
2000
IEEE
15 years 8 months ago
2000
IEEE
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...
147
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HPCA
2000
IEEE
15 years 8 months ago
2000
IEEE
Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in seco...
129
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ISORC
2000
IEEE
15 years 8 months ago
2000
IEEE
There have been many debates about the feasibility of providing guaranteed Quality of Service (QoS) when network traffic travels beyond the enterprise domain and into the vast unk...
117
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CAV
2000
Springer
15 years 8 months ago
2000
Springer
Abstract. Any formalmethodor tool is almostcertainlymoreoftenapplied in situationswheretheoutcomeis failure(acounterexample)rather than success (a correctness proof). We present a ...
196
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PLDI
1999
ACM
15 years 8 months ago
1999
ACM
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...