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» Quantifiers and Working Memory
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MICRO
1997
IEEE
108views Hardware» more  MICRO 1997»
15 years 2 months ago
Improving the Accuracy and Performance of Memory Communication Through Renaming
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
Gary S. Tyson, Todd M. Austin
JSSPP
1997
Springer
15 years 2 months ago
Memory Usage in the LANL CM-5 Workload
It is generally agreed that memory requirements should be taken into account in the scheduling of parallel jobs. However, so far the work on combined processor and memory schedulin...
Dror G. Feitelson
IJES
2007
71views more  IJES 2007»
14 years 9 months ago
Power management in external memory using PA-CDRAM
Abstract: Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose ...
Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mos...
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 8 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
CORR
2011
Springer
177views Education» more  CORR 2011»
14 years 5 months ago
Measuring NUMA effects with the STREAM benchmark
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated ph...
Lars Bergstrom