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ISCA
1997
IEEE
104views Hardware» more  ISCA 1997»
15 years 1 months ago
Complexity-Effective Superscalar Processors
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
Subbarao Palacharla, Norman P. Jouppi, James E. Sm...
ISCAPDCS
2007
14 years 11 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
107
Voted
HPCA
1995
IEEE
15 years 1 months ago
The Effects of STEF in Finely Parallel Multithreaded Processors
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
Yamin Li, Wanming Chu
PEPM
2009
ACM
15 years 6 months ago
Program interpolation
Program interpolation is a new type of transformation that given an input program written in a specially constructed Domain Specific Language (DSL), produces a family of function...
Andrew Moss, Dan Page
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 2 months ago
Parallel Processing Architectures for Reconfigurable Systems
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
Kees A. Vissers