352 search results - page 57 / 71 » Quantifying Instruction Criticality |
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HICSS
2011
IEEE
14 years 1 months ago
2011
IEEE
We propose XTRec, a primitive that can record the instruction-level execution trace of a commodity computing system. Our primitive is resilient to compromise to provide integrity ...
ICS
2007
Tsinghua U.
15 years 3 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
ASPLOS
2006
ACM
15 years 3 months ago
2006
ACM
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
MICRO
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Software energy estimation is a critical step in the design of energyefficient embedded systems. Instruction-level simulation techniques, despite several advances, remain too slo...