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DAC
2001
ACM
15 years 10 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
INFOCOM
2012
IEEE
13 years 9 days ago
A comparative study of architectural impact on BGP next-hop diversity
—Large ISPs have been growing rapidly in both the size and global connectivity. To scale with the sheer number of routers, many providers have replaced the flat full-mesh iBGP c...
Jong Han Park, Pei-chun Cheng, Shane Amante, Doria...
COMPSAC
2007
IEEE
15 years 4 months ago
Architecture-Based Software Reliability: Why Only a Few Parameters Matter?
Uncertainty analysis through sensitivity studies and quantification of the variance of the reliability estimate has become more common in architecture-based software reliability ...
Katerina Goseva-Popstojanova, Margaret Hamill
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 4 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
IPSN
2004
Springer
15 years 3 months ago
The impact of spatial correlation on routing with compression in wireless sensor networks
The efficacy of data aggregation in sensor networks is a function of the degree of spatial correlation in the sensed phenomenon. While several data aggregation (i.e., routing with...
Sundeep Pattem, Bhaskar Krishnamachari, Ramesh Gov...