4341 search results - page 268 / 869 » Quantitative Model checking |
126
Voted
CAV
2008
Springer
15 years 2 months ago
2008
Springer
Abstract. This paper develops a local reasoning method to check lineartime temporal properties of concurrent programs. In practice, it is often infeasible to model check over the p...
77
Voted
DATE
2010
IEEE
15 years 6 months ago
2010
IEEE
—Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Sp...
133
Voted
WOODPECKER
2001
15 years 2 months ago
2001
Ensuring that specifications are consistent is an important part of specification development and testing. In this paper we introduce the ConsVISor tool for consistency checking o...
128
Voted
ENTCS
2008
15 years 1 months ago
2008
Constraint automata have been used as an operational model for component connectors described in the coordination language Reo which specifies the cooperation and communication of...
167
Voted
DAC
2002
ACM
16 years 2 months ago
2002
ACM
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...