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ETS
2010
IEEE
174views Hardware» more  ETS 2010»
14 years 11 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
ICSE
2008
IEEE-ACM
15 years 11 months ago
An empirical study of the effects of test-suite reduction on fault localization
Fault-localization techniques that utilize information about all test cases in a test suite have been presented. These techniques use various approaches to identify the likely fau...
Yanbing Yu, James A. Jones, Mary Jean Harrold
HVC
2005
Springer
113views Hardware» more  HVC 2005»
15 years 3 months ago
Choosing Among Alternative Futures
Non-determinism is a serious impediment to testing and debugging concurrent programs. Such programs do not execute the same way each time they are run, which can hide the presence ...
Steve MacDonald, Jun Chen, Diego Novillo
82
Voted
TLCA
1993
Springer
15 years 2 months ago
Program Extraction from Normalization Proofs
This paper describes formalizations of Tait’s normalization proof for the simply typed λ-calculus in the proof assistants Minlog, Coq and Isabelle/HOL. From the formal proofs p...
Ulrich Berger
63
Voted
IIE
2006
84views more  IIE 2006»
14 years 10 months ago
On the Suitability of Programming Tasks for Automated Evaluation
Abstract. For many programming tasks we would be glad to have some kind of automatic evaluation process. As an example, most of the programming contests use an automatic evaluation...
Michal Forisek