147 search results - page 14 / 30 » Queue Machines: Hardware Compilation in Hardware |
115
Voted
SIGMETRICS
1996
ACM
15 years 1 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
110
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MICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
DATE
2010
IEEE
14 years 8 months ago
2010
IEEE
—Model-Based Development (MBD) provides an al level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic tr...
77
Voted
ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Blocked-execution multiprocessor architectures continuously run atomic blocks of instructions — also called Chunks. Such architectures can boost both performance and software pr...
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) with...