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» Queue Machines: Hardware Compilation in Hardware
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ASPLOS
1991
ACM
15 years 29 days ago
Code Generation for Streaming: An Access/Execute Mechanism
Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...
Manuel E. Benitez, Jack W. Davidson
IEEEPACT
2000
IEEE
15 years 1 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
SIGCSE
2005
ACM
102views Education» more  SIGCSE 2005»
15 years 3 months ago
Interpreting Java program runtimes
Many instructors use program runtimes to illustrate and reinforce algorithm complexity concepts. Hardware, operating system and compilers have historically influenced runtime resu...
Stuart A. Hansen
IEEEPACT
2006
IEEE
15 years 3 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
CASES
2000
ACM
15 years 1 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung