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» Queue Machines: Hardware Compilation in Hardware
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ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
15 years 1 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
ISPASS
2009
IEEE
15 years 4 months ago
Machine learning based online performance prediction for runtime parallelization and task scheduling
—With the emerging many-core paradigm, parallel programming must extend beyond its traditional realm of scientific applications. Converting existing sequential applications as w...
Jiangtian Li, Xiaosong Ma, Karan Singh, Martin Sch...
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
15 years 3 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
WISES
2003
14 years 10 months ago
Using a Java Optimized Processor in a Real World Application
— Java, a popular programming language on desktop systems, is rarely used in embedded systems. Some features of Java, like thread support in the language, could greatly simplify ...
Martin Schoeberl
IROS
2009
IEEE
170views Robotics» more  IROS 2009»
15 years 4 months ago
A programming architecture for smart autonomous underwater vehicles
— Autonomous underwater vehicles (AUVs) are an indispensable tool for marine scientists to study the world’s oceans. The Slocum glider is a buoyancy driven AUV designed for mis...
Hans C. Woithe, Ulrich Kremer