147 search results - page 18 / 30 » Queue Machines: Hardware Compilation in Hardware |
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
73
Voted
SAMOS
2007
Springer
15 years 3 months ago
2007
Springer
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
ISSS
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
HPCA
2008
IEEE
15 years 9 months ago
2008
IEEE
A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate ...