147 search results - page 19 / 30 » Queue Machines: Hardware Compilation in Hardware |
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
HICSS
1997
IEEE
15 years 1 months ago
1997
IEEE
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
COMPCON
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper describes Tempest, a collection of mechanisms for communication and synchronization in parallel programs. With these mechanisms, authors of compilers, libraries, and ap...
QNS
1996
14 years 10 months ago
1996
Inferno is an operating system well suited to applications that need to be portable, graphical, and networked. This paper describes the fundamental
oating point facilities of the...
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FDL
2003
IEEE
15 years 2 months ago
2003
IEEE
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...