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» Queue Machines: Hardware Compilation in Hardware
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ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 1 months ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...
IWMM
2009
Springer
152views Hardware» more  IWMM 2009»
15 years 4 months ago
A new approach to parallelising tracing algorithms
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt
CODES
2000
IEEE
15 years 1 months ago
Heterogeneous modeling and simulation of embedded systems in El Greco
This paper describes the functional specification and verification portions of El Greco, a system for high-level, heterogeneous functional specification, efficient compiled si...
Joseph Buck, Radha Vaidyanathan
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
14 years 9 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...
EUROPAR
2010
Springer
14 years 8 months ago
A Language-Based Tuning Mechanism for Task and Pipeline Parallelism
Abstract. Current multicore computers differ in many hardware aspects. Tuning parallel applications is indispensable to achieve best performance on a particular hardware platform....
Frank Otto, Christoph A. Schaefer, Matthias Dempe,...