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» Queue Machines: Hardware Compilation in Hardware
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USENIX
2001
14 years 10 months ago
Flexible Control of Parallelism in a Multiprocessor PC Router
SMP Click is a software router that provides both flexibility and high performance on stock multiprocessor PC hardware. It achieves high performance using device, buffer, and queu...
Benjie Chen, Robert Morris
ICS
1993
Tsinghua U.
15 years 1 months ago
Anatomy of a Message in the Alewife Multiprocessor
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
John Kubiatowicz, Anant Agarwal
98
Voted
CASES
2005
ACM
14 years 11 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
15 years 2 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
80
Voted
JCST
2008
94views more  JCST 2008»
14 years 9 months ago
Runtime Engine for Dynamic Profile Guided Stride Prefetching
Stride prefetching is recognized as an important technique to improve memory access performance. The prior work usually profiles and/or analyzes the program behavior offline, and u...
Qiong Zou, Xiao-Feng Li, Long-Bing Zhang