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» Queue Machines: Hardware Compilation in Hardware
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HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
15 years 29 days ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
75
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ASPLOS
2008
ACM
14 years 11 months ago
Streamware: programming general-purpose multicore processors using streams
Recently, the number of cores on general-purpose processors has been increasing rapidly. Using conventional programming models, it is challenging to effectively exploit these core...
Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Men...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 3 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
FCCM
2007
IEEE
108views VLSI» more  FCCM 2007»
15 years 3 months ago
Configurable Transactional Memory
Programming efficiency of heterogeneous concurrent systems is limited by the use of lock-based synchronization mechanisms. Transactional memories can greatly improve the programmi...
Christoforos Kachris, Chidamber Kulkarni
ICS
1993
Tsinghua U.
15 years 1 months ago
The NuMesh: A Modular, Scalable Communications Substrate
Many standardized hardware communication interfaces offer runtime flexibility and configurability at the cost of efficiency. An alternate approach is the use of a highly-effic...
Steve Ward, Karim Abdalla, Rajeev Dujari, Michael ...