Sciweavers

147 search results - page 8 / 30
» Queue Machines: Hardware Compilation in Hardware
Sort
View
ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
15 years 1 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
ASM
2008
ASM
14 years 11 months ago
Using EventB to Create a Virtual Machine Instruction Set Architecture
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine...
Stephen Wright
FPL
2009
Springer
154views Hardware» more  FPL 2009»
15 years 2 months ago
Compiler assisted runtime task scheduling on a reconfigurable computer
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems...
Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels
84
Voted
DYNAMO
2000
110views more  DYNAMO 2000»
14 years 10 months ago
Machine-adaptable dynamic binary translation
Dynamic binary translation is the process of translating and optimizing executable code for one machine to another at runtime, while the program is "executing" on the ta...
David Ung, Cristina Cifuentes
CAV
2000
Springer
125views Hardware» more  CAV 2000»
15 years 1 months ago
Efficient Reachability Analysis of Hierarchical Reactive Machines
Hierarchical state machines is a popular visual formalism for software specifications. To apply automated analysis to such specifications, the traditional approach is to compile th...
Rajeev Alur, Radu Grosu, Michael McDougall