147 search results - page 9 / 30 » Queue Machines: Hardware Compilation in Hardware |
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
ISSS
1996
IEEE
15 years 1 months ago
1996
IEEE
In the paper the problem of processor/compiler codesign for digital signal processing and embedded SYstems is discussed. The main principle we follow is the top-down approach char...
MICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
DATE
2008
IEEE
15 years 3 months ago
2008
IEEE
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...