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RSP
1998
IEEE
109views Control Systems» more  RSP 1998»
15 years 3 months ago
A Technique for Combined Virtual Prototyping and Hardware Design
A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the ...
Patrick Schaumont, Geert Vanmeerbeeck, E. Watzeels...
ERSA
2006
109views Hardware» more  ERSA 2006»
15 years 1 months ago
Synthesis of Object Oriented Models on Reconfigurable Hardware
Abstract-- In this work the problem of modeling reconfigurable systems behavior with a precise, executable semantics is considered. The possibility of synthesising such models onto...
Giovanni Agosta, Francesco Bruschi, Marco D. Santa...
FPL
2004
Springer
143views Hardware» more  FPL 2004»
15 years 3 months ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
ISCAS
2008
IEEE
127views Hardware» more  ISCAS 2008»
15 years 6 months ago
Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection
— ICEBERG is a block cipher that has been recently proposed for security applications requiring efficient FPGA implementations. In this paper, we investigate a compact ASIC imple...
Huiju Cheng, Howard M. Heys
IFIP12
2009
14 years 9 months ago
TELIOS: A Tool for the Automatic Generation of Logic Programming Machines
In this paper the tool TELIOS is presented, for the automatic generation of a hardware machine, corresponding to a given logic program. The machine is implemented using an FPGA, wh...
Alexandros C. Dimopoulos, Christos Pavlatos, Georg...