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ISSS
2000
IEEE
144views Hardware» more  ISSS 2000»
15 years 4 months ago
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
ISPD
2006
ACM
102views Hardware» more  ISPD 2006»
15 years 5 months ago
A faster implementation of APlace
APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and densi...
Andrew B. Kahng, Qinke Wang
EUROMICRO
2009
IEEE
15 years 6 months ago
A Component-Based Technology for Hardware and Software Components
One of the challenges in development of embedded systems is to cope with hardware and software components simultaneously. Often is their integration cumbersome due to their incomp...
Luka Lednicki, Ana Petricic, Mario Zagar
IMA
2007
Springer
129views Cryptology» more  IMA 2007»
15 years 6 months ago
Toward Acceleration of RSA Using 3D Graphics Hardware
Demand in the consumer market for graphics hardware that accelerates rendering of 3D images has resulted in commodity devices capable of astonishing levels of performance. These re...
Andrew Moss, Dan Page, Nigel P. Smart
3DPVT
2006
IEEE
233views Visualization» more  3DPVT 2006»
15 years 6 months ago
Scanline Optimization for Stereo on Graphics Hardware
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
Christopher Zach, Mario Sormann, Konrad F. Karner