5762 search results - page 131 / 1153 » R-tree: A Hardware Implementation |
171
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APCCAS
2006
IEEE
16 years 10 days ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
113
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ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes the hardware design and implementation of the JAWS (Just Another Watermarking System) embedder and detector for watermarking of realtime uncompressed digital ...
163
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ISMVL
1998
IEEE
15 years 10 months ago
1998
IEEE
Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider issues regarding the efficient implementation of a...
120
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ISCAS
1993
IEEE
15 years 10 months ago
1993
IEEE
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
119
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IFIP
1992
Springer
15 years 10 months ago
1992
Springer
In microarchitecure synthesis, early algorithms considered only a single implementation technique for IF -statements. Focus was on scheduling and on maximum hardware sharing. In t...