5762 search results - page 133 / 1153 » R-tree: A Hardware Implementation |
134
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DATE
2006
IEEE
16 years 10 days ago
2006
IEEE
Recently, the interest about the Tate pairing over binary fields has decreased due to the existence of efficient attacks to the discrete logarithm problem in the subgroups of su...
133
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ISCAS
2006
IEEE
16 years 9 days ago
2006
IEEE
Abstract— This paper introduces a novel four-order system, which can generate one-directional (1-D) n−torus, twodirectional (2-D) n × m −torus, three-directional (3-D) n × ...
155
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MSS
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
161
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ISCAS
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents an algorithm for the low power implementation of the Discrete Cosine Transform on Single multiplier CMOS DSPs. The algorithm reduces power by a combination of ...
176
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CAV
1998
Springer
15 years 10 months ago
1998
Springer
An implementation of an out-of-order processing unit based on Tomasulo's algorithm is formally verified using compositional model checking techniques. This demonstrates that f...