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ITNG
2010
IEEE
14 years 10 months ago
2010
IEEE
—The increase in computational power of off-the-shelf hardware offers more and more advantageous tradeoffs among efficiency, cost and availability, thus enhancing the feasibil...
MICRO
2000
IEEE
14 years 11 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
CIMAGING
2009
14 years 9 months ago
2009
Color image demosaicking is a key process in the digital imaging pipeline. In this paper, we present a rigorous treatment of a classical demosaicking algorithm based on alternatin...
FPL
2010
Springer
14 years 9 months ago
2010
Springer
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
ERSA
2009
14 years 9 months ago
2009
An increasing number of embedded system solutions in space, military, and consumer electronics applications rely on processor cores inside reconfigurable logic devices. Ensuring da...