Sciweavers

5762 search results - page 44 / 1153
» R-tree: A Hardware Implementation
Sort
View
SSD
1999
Springer
97views Database» more  SSD 1999»
15 years 4 months ago
A Performance Evaluation of Spatial Join Processing Strategies
We provide an evaluation of query execution plans (QEP) in the case of queries with one or two spatial joins. The QEPs assume R -tree indexed relations and use a common set of spat...
Apostolos Papadopoulos, Philippe Rigaux, Michel Sc...
CONIELECOMP
2011
IEEE
14 years 3 months ago
FPGA design and implementation for vertex extraction of polygonal shapes
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
Jorge Martínez-Carballido, Jorge Guevara-Es...
DSD
2010
IEEE
133views Hardware» more  DSD 2010»
14 years 9 months ago
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
Igor Lemberski, Petr Fiser
DATE
2008
IEEE
110views Hardware» more  DATE 2008»
15 years 6 months ago
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA
Philippe Bonnot, Fabrice Lemonnier, Gilbert Edelin...
ISCAS
2008
IEEE
123views Hardware» more  ISCAS 2008»
15 years 6 months ago
Address compression for scalable load/store queue implementation
Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen