5762 search results - page 47 / 1153 » R-tree: A Hardware Implementation |
ISCAS
1994
IEEE
15 years 3 months ago
1994
IEEE
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
DSD
2007
IEEE
15 years 1 months ago
2007
IEEE
169
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ARC
2012
Springer
13 years 7 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
116
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JSA
2002
14 years 11 months ago
2002
This paper examines some models of FSMs that can be implemented in dynamically and statically reconfigurable FPGAs. They enable circuits for the FSMs to be constructed in such a wa...