5762 search results - page 59 / 1153 » R-tree: A Hardware Implementation |
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FPL
2009
Springer
15 years 4 months ago
2009
Springer
Reconfigurable systems are widely used nowadays to increase performance of computationally intensive applications. There exist a lot of synthesis tools that automatically generate...
FPL
2008
Springer
15 years 1 months ago
2008
Springer
This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
ISCAS
2008
IEEE
15 years 6 months ago
2008
IEEE
— In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/I...
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FSE
2004
Springer
15 years 3 months ago
2004
Springer
Abstract. We present a fast involutional block cipher optimized for reconfigurable hardware implementations. ICEBERG uses 64-bit text blocks and 128-bit keys. All components are in...
148
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FPGA
2008
ACM
15 years 1 months ago
2008
ACM
Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality ps...