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DCC
2008
IEEE
15 years 1 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
ARC
2009
Springer
142views Hardware» more  ARC 2009»
15 years 6 months ago
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem
Abstract. This paper presents implementation results of a reconfigurable elliptic curve processor defined over prime fields GF(p). We use this processor to compare a new algorit...
Brian Baldwin, Richard Moloney, Andrew Byrne, Gary...
FPT
2005
IEEE
133views Hardware» more  FPT 2005»
15 years 5 months ago
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator
Two FPGA implementations of a Shape Adaptive Discrete Cosine Transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used...
Andrew Kinane, Alan Casey, Valentin Muresan, Noel ...
DNA
2007
Springer
106views Bioinformatics» more  DNA 2007»
15 years 3 months ago
Hardware Acceleration for Thermodynamic Constrained DNA Code Generation
Reliable DNA computing requires a large pool of oligonucleotides that do not produce cross-hybridize. In this paper, we present a transformed algorithm to calculate the maximum wei...
Qinru Qiu, Prakash Mukre, Morgan Bishop, Daniel J....
TVLSI
2008
132views more  TVLSI 2008»
14 years 11 months ago
Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware
Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the fl...
Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M....