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ICES
2007
Springer
83views Hardware» more  ICES 2007»
15 years 6 months ago
Extrinsic Evolvable Hardware on the RISA Architecture
The RISA Architecture is a novel reconfigurable hardware platform containing both hardware and software reconfigurable elements. This paper describes the architecture and the fea...
Andrew J. Greensted, Andrew M. Tyrrell
FCCM
1997
IEEE
106views VLSI» more  FCCM 1997»
15 years 3 months ago
Fault simulation on reconfigurable hardware
In this paper we introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. Our performance estimate shows that ou...
Miron Abramovici, Premachandran R. Menon
ESANN
2008
15 years 1 months ago
Neural network hardware architecture for pattern recognition in the HESS2 project
In this paper, we consider the problem of implementation of neural network in the context of the level 2 trigger of HESS2 project. We propose a hardware architecture which which ta...
Narayanan Ramanan, Sonia Khatchadourian, Jean-Chri...
CGF
2002
156views more  CGF 2002»
14 years 11 months ago
Object Space EWA Surface Splatting: A Hardware Accelerated Approach to High Quality Point Rendering
Elliptical weighted average (EWA) surface splatting is a technique for high quality rendering of point-sampled 3D objects. EWA surface splatting renders water-tight surfaces of co...
Liu Ren, Hanspeter Pfister, Matthias Zwicker
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
15 years 6 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...